1. Field of the Invention
The present invention relates to a semiconductor integrated circuit that generates two or more waveforms out of phase by a desired phase difference.
2. Description of the Prior Art
FIG. 9 is a circuit block diagram showing a prior art semiconductor integrated circuit that generates two waveforms 90xc2x0 out of phase. In the figure, reference numeral 1 denotes an amplifier such as a differential amplifier, for outputting both an input signal LOIN and the inversion of the input signal, numeral 2 denotes an RC phase shifter for shifting the phase of a differential signal from the amplifier 1 to advance the phase of the differential signal, numeral 3 denotes a CR phase shifter for shifting the phase of the differential signal to delay the phase of the differential signal, numerals 4 and 5 denote front-end amplifiers, such as differential amplifiers, for amplifying the output signals from the RC phase shifter 2 and the CR phase shifter 3, those signal being 90xc2x0 out of phase, respectively, numerals 6 and 7 denote adders for obtaining the sum of signal vectors from the front-end amplifiers 4 and 5, reference numeral 8 and 9 denotes back-end amplifiers for amplifying the signals output from the adders 6 and 7 respectively, those signals being 90xc2x0 out of phase, and for outputting an output signal I and the inversion of the output signal I, and another output signal Q and the inversion of the other output signal Q, those signals I and Q being 90xc2x0 out of phase.
FIGS. 10(a) to 10(d) are explanatory drawings showing the phases of signals at each node of the prior art semiconductor integrated circuit.
In operation, the amplifier 1 converts an input signal LOIN into differential signals S and SB and outputs them, as shown in FIG. 10(a). The RC phase shifter 2 shifts the phases of those differential motion signals S and SB so as to advance the phases of the differential motion signals S and SB, and the CR phase shifter 3 shifts the phases of the differential signals S and SB so as to delay the phases of the differential motion signals S and SB. FIG. 10(b) shows the case where only the differential signal S is shifted to a signal R by the C phase shifter 2, and is also shifted to a signal C by the CR phase shifter 3. Here, the RC phase shifter 2 and the CR phase shifter 3 perform a phase-shift of 45 degrees and a phase-shift of xe2x88x9245 degrees on the respective inputs when the input signal LOIN has a frequency lies within a certain frequency range in which the time constant of the RC phase shifter 2 agrees with that of the CR phase shifter 3. The output signal R of the RC phase shifter 2 and the output signal C of the CR phase shifter 3 are thus 90xc2x0 out of phase. However, since the phase-shift angles and the signal amplitudes of both are deviated from their desired ones, and therefore the orthogonalization relationship between the signals R and C cannot be maintained, the deviations have to be corrected with the circuit following the RC phase shifter 2 and the CR phase shifter 3 when the input signal LOIN has a frequency in which the time constant of the RC phase shifter 2 does not agree with that of the CR phase shifter 3.
The front-end amplifiers 4 and 5 limit the amplitudes of the signal R from the RC shifter 2 and the signal C from the CR shifter 3 by amplifying the amplitudes, respectively, so as to equate the amplitudes of those signals. The adders 6 and 7 calculates the sum of the two equal-amplitude signal vectors from the front-end amplifiers 4 and 5.
Both a signal RB+C that is the sum of the inversion RB of the signal vector R and the signal vector C obtained by the adder 6, and a signal R+C that is the sum of the signal vector R and the signal vector C obtained by the adder 7 are shown in FIG. 10(c). The angle between the signal RB+C and the signal R+C is 90 degrees.
In addition, the back-end amplifiers 8 and 9 amplifies the amplitudes of the signal RB+C from the adder 6 and the signal R+C from the adder 7, respectively, so as to limit the amplitudes of those signals, and outputs two output signals I and Q which are equal in amplitude and 90xc2x0 out of phase, and the respective inversions of I and Q. As shown in FIG. 10(d), the amplitude of the signal RB+C is limited by the back-end amplifier 8 and is then phase-shifted, so that the output signal I is generated, and the amplitude of the signal B+C is limited by the back-end amplifier 9 and is then phase-shifted, so that the output signal Q is generated.
Such a prior art technology is disclosed by I. A. Koullias et al., xe2x80x9cA 900 MHz Transceiver Chip Set for Dual-Mode Cellular Radio Mobile Terminalsxe2x80x9d, ISSCC Dig. of Tech. Papers, pp.140-141, February 1993, for example.
A problem with prior art semiconductor integrated circuits constructed as above is that if the two signals input to each of the adders 6 and 7 are not equal in amplitude, each of the adders 6 and 7 cannot normally calculate the sum of the two vectors applied thereto. Furthermore, although the two output signals I and Q only have to mutually have the phase difference of 90 degrees, the amplitude error of those signals should be minimized because those signals are evaluated as vectors.
Therefore, to minimize the amplitude error of those signals, it is necessary to construct the front-end amplifiers 4 and 5 and the back-end amplifiers 8 and 9 using transistors having, a larger size and a larger amount of current, and this results in an increase in the chip area and the difficulty in reduction of the amount of current flowing the semiconductor integrated circuit.
The present invention is proposed to solve the above problems. It is therefore an object to provide a semiconductor integrated circuit for generating two or more waveforms out of phase by a desired phase difference, capable of decreasing its chip area and reducing the amount of current flowing therein.
In accordance with an aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a phase control unit for shifting the phase of an input signal by two or more different fixed phases so as to generate two or more output signals out of phase; and a phase detector for detecting phase differences among the two or more output signals from the phase control unit, for generating one or more correction signals each having a value corresponding to a deviation of one of the detected phase differences from a desired phase difference, and for feeding the one or more correction signals back to the phase control unit so as to make the detected phase differences equal to desired phase differences, respectively.
In accordance with another aspect of the present invention, the phase control unit includes: a first phase shifter for shifting the phase of the input signal by a fixed phase; a second phase shifter for shifting the phase of the input signal by a fixed phase; a variable capacitor for capacity adjustment connected in parallel to the first phase shifter and having a control terminal; a first amplifier connected to the first phase shifter; and a second amplifier connected to the second phase shifter. And, the phase detector includes: a mixer circuit for multiplying an output signal of the first amplifier by an output signal of the second amplifier; a reference voltage generation circuit for generating a reference voltage corresponding to a desired phase difference; and a charge pump circuit for generating a correction signal having a value corresponding to a difference between a multiplication result from the mixer circuit and the reference voltage from the reference voltage generation circuit, and for feeding the correction signal to the control terminal of the variable capacitor.
In accordance with a further aspect of the present invention, the phase control unit includes: a first phase shifter for shifting the phase of the input signal by a fixed phase; a second phase shifter for shifting the phase of the input signal by a fixed phase; a first amplifier connected to the first phase shifter and provided with a variable capacitor for capacity adjustment connected to an output terminal thereof and having a control terminal; a second amplifier connected to the first amplifier; and a third amplifier connected to the second phase shifter. And, the phase detector includes: a mixer circuit for multiplying an output signal of the second amplifier by an output signal of the third amplifier; a reference voltage generation circuit for generating a reference voltage corresponding to a desired phase difference; and a charge pump circuit for generating a correction signal having a value corresponding to a difference between a multiplication result from the mixer circuit and the reference voltage from the reference voltage generation circuit, and for feeding the correction signal to the control terminal of the variable capacitor.
In accordance with another aspect of the present invention, the phase control unit includes: a first phase shifter for shifting the phase of the input signal by a fixed phase; a second phase shifter for shifting the phase of the input signal by a fixed phase; a first variable capacitor for capacity adjustment connected in parallel to the first phase shifter and having a control terminal; a second variable capacitor for capacity adjustment connected in parallel to the second phase shifter and having a control terminal; a first amplifier connected to the first phase shifter; and a second amplifier connected to the second phase shifter. And, the phase detector includes: a mixer circuit for multiplying an output signal of the first amplifier by an output signal of the second amplifier; a reference voltage generation circuit for generating a reference voltage corresponding to a desired phase difference; and a charge pump circuit for generating first and second correction signals of opposite polarity having a value corresponding to a difference between a multiplication result from the mixer circuit and the reference voltage from the reference voltage generation circuit, and for feeding the first and second correction signal to the control terminals of the first and second variable capacitors, respectively.
In accordance with a further aspect of the present invention, the phase control unit includes: a first phase shifter for shifting the phase of the input signal by a fixed phase; a second phase shifter for shifting the phase of the input signal by a fixed phase; a first amplifier connected to the first phase shifter and provided with a variable capacitor for capacity adjustment connected to an output terminal thereof and having a control terminal; a second amplifier connected to the first amplifier; a third amplifier connected to the second phase shifter and provided with a variable capacitor for capacity adjustment connected to an output terminal thereof and having a control terminal; and a fourth amplifier connected to the third amplifier. And, the phase detector includes: a mixer circuit for multiplying an output signal of the second amplifier by an output signal of the fourth amplifier; a reference voltage generation circuit for generating a reference voltage corresponding to a desired phase difference; and a charge pump circuit for generating first and second correction signals of opposite polarity having a value corresponding to a difference between a multiplication result from the mixer circuit and the reference voltage from the reference voltage generation circuit, and for feeding the first and second correction signals to the control terminals of the variable capacitors of the first and third amplifiers, respectively.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.